library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


-- synopsys translate_off
library UNISIM;
use UNISIM.vcomponents.all;
-- synopsys translate_on


entity ramtest is port
  ( clk50_in : in std_logic;
    led_out : out std_logic_vector (7 downto 0);
    -- 4 push button inputs
    pb_in   : in std_logic_vector(3 downto 0);
    -- SRAM ports
    sram_ce1_out  : out std_logic;
    sram_ub1_out  : out std_logic;
    sram_lb1_out  : out std_logic;
    sram_we_out   : out std_logic;
    sram_oe_out   : out std_logic;
    sram_a_out    : out std_logic_vector(17 downto 0);
    sram_io :  inout std_logic_vector(15 downto 0)
);
end ramtest;

architecture Behavioral of ramtest is

-- 50 Mhz clock (creates 20ns cycles)
signal clk50             : std_logic;
signal clk50_before_dll  : std_logic;
signal clk50_int         : std_logic;
signal clk50_non_g       : std_logic;

-- led
signal led : std_logic_vector (7 downto 0);

-- push button signal
signal pb 		 : std_logic_vector(3 downto 0);
signal rst 		 : std_logic;
signal sram_ce1      : std_logic
                     :='1';
signal sram_oe       : std_logic
                     :='1';
signal sram_we       : std_logic
                     :='1';
signal iobuf_t       : std_logic
                     :='0';
signal read_addr     : std_logic_vector(6 downto 0)
                     := "0000000";
signal write_addr    : std_logic_vector(6 downto 0)
                     := "0000000";

-- where to read data from memory
signal sram_data_read  : std_logic_vector(15 downto 0);
-- where to write data in memory
signal sram_data_write : std_logic_vector(15 downto 0);
-- location to write the desired address
signal sram_addr     : std_logic_vector(17 downto 0)
                     := "000000000000000000";
signal high_value    : std_logic
                     := '1' ;
signal low_value     : std_logic
                     := '0';
-- a counter to generate some events.
signal ctr           : std_logic_vector(2 downto 0)
                     := "000";
-- a counter to display data
signal ctr_display : std_logic_vector (25 downto 0)
              := "00000000000000000000000000";


component OBUF_LVCMOS33 port
 ( O : out std_logic;
   I : in std_logic);
end component;

component ibufg port
 ( O : out std_logic;
   I : in std_logic);
end component;

-- CMOS33 input buffer primitive
component ibuf_lvcmos33 port
 (i : in std_logic;
  o : out std_logic);
end component;

component IOBUF_LVCMOS33 port
 ( O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic);
end component;

component CLKDLL
 port (
   CLK0 : out std_logic;
   CLK90 : out std_logic;
   CLK180 : out std_logic;
   CLK270 : out std_logic;
   CLK2X : out std_logic;
   CLKDV : out std_logic;
   LOCKED : out std_logic;
   CLKIN : in std_logic;
   CLKFB : in std_logic;
   RST : in std_logic
 );
end component;

component ibufg_lvcmos33 port
  (i : in std_logic;
   o : out std_logic);
end component;

component bufg port
  (i : in std_logic;
   o : out std_logic);
end component;


begin

rst <= pb(0);
high_value <= '1';
low_value <= '0';

-- this CLKDLL component
-- generates the clk100 signal from the clk50_in signal
dll0 : CLKDLL port map 
  (CLKIN => clk50_before_dll,
   CLKFB => clk50,
   RST => low_value,
   CLK0 => clk50_non_g,
   CLK90 => OPEN,
   CLK180 => OPEN,			     
   CLK270 => OPEN,
   CLK2X => OPEN,
   CLKDV => OPEN,
   LOCKED => OPEN);
   
clk50in_ibuf : ibufg_lvcmos33	port map
  ( i => clk50_in,
    o => clk50_int );
rxclka_bufg : bufg port map
  ( i => clk50_int,
    o => clk50_before_dll ) ;
rxclk100_bufg : bufg port map
  ( i => clk50_non_g,
    o => clk50 ) ;

g3 : FOR i IN 0 to 3 generate
pb_ibuf 	: ibuf_lvcmos33 port map
 ( i => pb_in(i),
   o => pb(i));
end generate g3;

sram_lb1_out <= '0';
sram_ub1_out <= '0';

g1 : FOR i IN sram_io'RANGE generate
  iod0 : IOBUF_LVCMOS33 port map 
  (I => sram_data_write(i),
   IO => sram_io(i),
   O => sram_data_read(i),
   T => iobuf_t);
end generate g1;
	 
ledobuf1 : for i in 0 to 7 generate
  led_obuf : obuf_lvcmos33 port map
    (i => led(i),
    	o => led_out(i));
end generate ;

g2 : FOR i IN sram_a_out'RANGE generate
  oa0 : OBUF_LVCMOS33 port map
  (O => sram_a_out(i),
   I => sram_addr(i));
end generate g2;

we : OBUF_LVCMOS33 port map
  (O => sram_we_out,
   I => sram_we);
oe : OBUF_LVCMOS33 port map
  (O => sram_oe_out,
   I => sram_oe);
ce1 : OBUF_LVCMOS33 port map
  (O => sram_ce1_out,
   I => sram_ce1);

process (clk50) 
begin
  if clk50'event and clk50='1' then
    ctr_display<=ctr_display+"00000000000000000000000001";
    if ctr_display="00001011111010111100001000" then
      ctr_display<="00000000000000000000000000";
    end if;
    if rst='1' then
      led <="00000000";
      ctr_display<="00000000000000000000000000";
      read_addr<="0000000";
      write_addr<="0000000";
      sram_addr <= "000000000000000000";
      sram_data_write <= "0000000000000000";
      ctr <= "000";
      sram_oe <= '1';
      sram_ce1 <= '1';
      sram_we <= '0';
    else
	 led(7) <= read_addr(0);
      if ctr="000" then
        -- step 1 address controlled memory read
	   iobuf_t <= '1';
        sram_addr <= "00000100001"&read_addr;
        sram_oe <= '0';
        sram_ce1 <= '0';
	   sram_we <= '1';			 
	   ctr <= "001";
      elsif ctr="001" then
        -- step 2 reset stuff and read values
	   iobuf_t <= '0';
        sram_addr <= "00000100001"&read_addr;
        sram_oe <= '0';
        sram_ce1 <= '1'; -- disable sram
	   sram_we <= '1';
        if ctr_display="00000000000000000000000000" then
	     read_addr<=read_addr+"000001";
        end if;
	   ctr <= "010";        

	   led(0) <= sram_data_read(0);
        led(1) <= sram_data_read(1);
        led(2) <= sram_data_read(2);        
	   led(3) <= sram_data_read(3);
        led(4) <= sram_data_read(4);
        led(5) <= sram_data_read(5);

      elsif ctr="010" then
        -- step 3 WE controlled write to memory
	   --         with OE low during write cycle
	   iobuf_t <= '0';
        sram_addr <= "00000100001"&write_addr;
        sram_oe <= '0';
        sram_ce1 <= '0';
	   sram_we <= '0';
        sram_data_write <= "111111111"&write_addr;
	   ctr <= "011";	    
      elsif ctr="011" then
        -- step 4 clear everything and disable sram
	   iobuf_t <= '0';
        sram_addr <= "000000000000000000";
        sram_oe <= '0';
        sram_ce1 <= '1';
	   sram_we <= '1';
        sram_data_write <= "0000000000000000";
	   ctr <= "000";
      else 
        ctr <= "000";
      end if;
    end if; -- rst='1'
  end if;
end process;

end Behavioral;